URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 72

Rev	Log message	Author	Age	Path
72	Project management folder.	creep	5620d 12h	/
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5620d 12h	/
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	5624d 08h	/
69	Added signal origin/destination.	creep	5624d 10h	/
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5624d 10h	/
67	File name change to lowercase. HAL says so!	creep	5624d 12h	/
66	File name change to lowercase. HAL says so!	creep	5624d 12h	/
65	Now the blocks are connected.	gabrieloshiro	5625d 07h	/
64	Constant were wrong.	gabrieloshiro	5625d 07h	/
63	Fixed several HAL warnings. Still plenty to do.	creep	5625d 07h	/
62	The DUT file name changed.	creep	5625d 07h	/
61	File name change to lowercase. HAL says so!	creep	5625d 08h	/
60	File name change. HAL says so!	creep	5625d 08h	/
59	I`ve fixed some latch creation.	gabrieloshiro	5625d 08h	/
58	ALU with all opcodes ready for simulation.	gabrieloshiro	5625d 09h	/
57	A very simple testbench that checks the execution for a single instruction, i.e. no memory.	creep	5625d 09h	/
56	Several changes in the output logic to respect the pipelining.	creep	5625d 09h	/
55	ALU has all opcodes now! Comments inside ALU are completely wrong.	gabrieloshiro	5625d 10h	/
54	Processor Status register modified.	gabrieloshiro	5625d 12h	/
53	Added default header.	creep	5625d 17h	/