OpenCores
URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] - Rev 14

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4428d 04h /
13 Forgot about the new library I added earlz 4428d 06h /
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD
earlz 4428d 07h /
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4431d 20h /
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4431d 21h /
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4432d 04h /
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing
earlz 4433d 04h /
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)
earlz 4433d 05h /
6 Reworked memory code to hopefully synthesize better earlz 4433d 10h /
5 Modified registerfile to be dual-port for both read and write earlz 4433d 21h /
4 Added internal memory interface
Updated design
earlz 4434d 05h /
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming
earlz 4434d 21h /
2 Initial commit earlz 4434d 22h /
1 The project and the structure was created root 4435d 00h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.