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15 Added README, LICENSE, and the (so far not created) incdec component earlz 4433d 21h /
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4434d 05h /
13 Forgot about the new library I added earlz 4434d 07h /
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD
earlz 4434d 08h /
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4437d 21h /
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4437d 22h /
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4438d 06h /
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing
earlz 4439d 05h /
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)
earlz 4439d 06h /
6 Reworked memory code to hopefully synthesize better earlz 4439d 11h /
5 Modified registerfile to be dual-port for both read and write earlz 4439d 22h /
4 Added internal memory interface
Updated design
earlz 4440d 06h /
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming
earlz 4440d 22h /
2 Initial commit earlz 4440d 23h /
1 The project and the structure was created root 4441d 02h /

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