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Rev	Log message	Author	Age	Path
23	Added top module for testing how our memory and cpu will work together. (hint: success) Messing around with a small timing issue in core	earlz	4391d 11h	/
22	Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch	earlz	4392d 03h	/
21	The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it.	earlz	4392d 03h	/
20	fuck it. All sorts of broken, will try to fix it tomorrow	earlz	4393d 03h	/
19	Got beginning of core/decoder for the CPU	earlz	4393d 04h	/
18	Finished memory controller	earlz	4396d 14h	/
17	Added fetch component for fetching from memory to instruction register Added additional testing for carryover to make sure it's correct	earlz	4397d 04h	/
16	Renamed incdec to carryover (see design for why). carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.	earlz	4400d 06h	/
15	Added README, LICENSE, and the (so far not created) incdec component	earlz	4402d 03h	/
14	Added ALU with all the operations we'll need. Synthesizes as well trivially	earlz	4402d 11h	/
13	Forgot about the new library I added	earlz	4402d 14h	/
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4402d 15h	/
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4406d 04h	/
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4406d 05h	/
9	Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench	earlz	4406d 12h	/
8	Added blockram for inferring actual block RAM. Now we need a memory controller, not a crappy memory emulation thing	earlz	4407d 12h	/
7	Changed memory to fix bound check error Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)	earlz	4407d 13h	/
6	Reworked memory code to hopefully synthesize better	earlz	4407d 17h	/
5	Modified registerfile to be dual-port for both read and write	earlz	4408d 05h	/
4	Added internal memory interface Updated design	earlz	4408d 13h	/

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[/] - Rev 23

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