URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 36

Rev	Log message	Author	Age	Path
36	Removed default instruction decode	ghutchis	7174d 07h	/
35	Updated IO registers to add checksum and increment-on-read registers used for testing block I/O instructions.	ghutchis	7174d 18h	/
34	Created test for block I/O instructions	ghutchis	7174d 18h	/
33	Added missing IncDec controls to OUTI/OUTD instructions	ghutchis	7175d 15h	/
32	Added "bintr" basic interrupt test, which tests Z80 interrupt mode 1.	ghutchis	7190d 18h	/
31	1) Added environment support for Z80 op decode in log file. 2) Fixed env support for interrupt generation and clearing	ghutchis	7190d 18h	/
30	Added HTML version of docs	ghutchis	7193d 17h	/
29	Added references	ghutchis	7193d 17h	/
28	Added code to initialize RAM to all 00 at environment start-up time.	ghutchis	7193d 18h	/
27	Modified tvs80 test to run from a ROM image, and work with the standard environment.	ghutchis	7193d 18h	/
26	Updated docs	ghutchis	7193d 18h	/
25	Added XML master document	ghutchis	7193d 20h	/
24	tv80s.v	ghutchis	7204d 07h	/
23	Completed conversion to one-hot encoding	ghutchis	7216d 21h	/
22	Changed starting state for one-hot tstate	ghutchis	7216d 21h	/
21	Replaced encoded states with one-hot	ghutchis	7217d 22h	/
20	Merged suggested patches from HPA into test branch	ghutchis	7239d 10h	/
19	This commit was manufactured by cvs2svn to create branch 'hpa1'.		7253d 01h	/
18	Updated verification status document	ghutchis	7253d 01h	/
17	Added many additional debug messages. All tests now pass up until rst (bit reset) instructions.	ghutchis	7253d 01h	/