URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 41

Rev	Log message	Author	Age	Path
41	Added random-read value port	ghutchis	7172d 16h	/
40	Added random-read port and block memory instruction test	ghutchis	7172d 16h	/
39	Added checksum port definitions, and test for block-OUT instructions	ghutchis	7172d 17h	/
38	Added command-line options for help (-h) and run with instruction decode (-d)	ghutchis	7174d 09h	/
37	Added new I/O registers for testing block I/O	ghutchis	7174d 10h	/
36	Removed default instruction decode	ghutchis	7174d 10h	/
35	Updated IO registers to add checksum and increment-on-read registers used for testing block I/O instructions.	ghutchis	7174d 21h	/
34	Created test for block I/O instructions	ghutchis	7174d 21h	/
33	Added missing IncDec controls to OUTI/OUTD instructions	ghutchis	7175d 18h	/
32	Added "bintr" basic interrupt test, which tests Z80 interrupt mode 1.	ghutchis	7190d 20h	/
31	1) Added environment support for Z80 op decode in log file. 2) Fixed env support for interrupt generation and clearing	ghutchis	7190d 20h	/
30	Added HTML version of docs	ghutchis	7193d 20h	/
29	Added references	ghutchis	7193d 20h	/
28	Added code to initialize RAM to all 00 at environment start-up time.	ghutchis	7193d 20h	/
27	Modified tvs80 test to run from a ROM image, and work with the standard environment.	ghutchis	7193d 20h	/
26	Updated docs	ghutchis	7193d 21h	/
25	Added XML master document	ghutchis	7193d 23h	/
24	tv80s.v	ghutchis	7204d 10h	/
23	Completed conversion to one-hot encoding	ghutchis	7217d 00h	/
22	Changed starting state for one-hot tstate	ghutchis	7217d 00h	/