OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 46

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
46 This commit was manufactured by cvs2svn to create branch 'restruc1'. 7293d 07h /
45 Added negedge version of top ghutchis 7293d 07h /
44 Updated run script for better dump control ghutchis 7293d 10h /
43 Fixed assembly routines for blk mem copy test ghutchis 7315d 23h /
42 Added decode of OUT (##),A instruction
Removed dump-by-default and added DUMP_START define
ghutchis 7315d 23h /
41 Added random-read value port ghutchis 7318d 03h /
40 Added random-read port and block memory instruction test ghutchis 7318d 03h /
39 Added checksum port definitions, and test for block-OUT instructions ghutchis 7318d 04h /
38 Added command-line options for help (-h) and run with instruction decode (-d) ghutchis 7319d 21h /
37 Added new I/O registers for testing block I/O ghutchis 7319d 21h /
36 Removed default instruction decode ghutchis 7319d 21h /
35 Updated IO registers to add checksum and increment-on-read registers
used for testing block I/O instructions.
ghutchis 7320d 08h /
34 Created test for block I/O instructions ghutchis 7320d 08h /
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7321d 05h /
32 Added "bintr" basic interrupt test, which tests Z80 interrupt mode 1. ghutchis 7336d 07h /
31 1) Added environment support for Z80 op decode in log file.
2) Fixed env support for interrupt generation and clearing
ghutchis 7336d 07h /
30 Added HTML version of docs ghutchis 7339d 07h /
29 Added references ghutchis 7339d 07h /
28 Added code to initialize RAM to all 00 at environment start-up time. ghutchis 7339d 07h /
27 Modified tvs80 test to run from a ROM image, and work with the
standard environment.
ghutchis 7339d 07h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.