URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 81

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Rev	Log message	Author	Age	Path
81	Initial version of TV80 Wishbone Wrapper	hharte	5685d 05h	/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6784d 18h	/
79	Added JR self-checking test	ghutchis	6784d 18h	/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6827d 19h	/
77	Added back files lost after server crash	ghutchis	6859d 13h	/
76	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6938d 19h	/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6938d 19h	/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6938d 20h	/
73	Added RC4 encrypt/decrypt test	ghutchis	6950d 15h	/
72	Added copyright header	ghutchis	6950d 15h	/
71	Ported UART from T80	ghutchis	7011d 19h	/
70	Added test for T16450 UART	ghutchis	7062d 14h	/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7062d 14h	/
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7070d 14h	/
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7070d 14h	/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7070d 14h	/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7070d 14h	/
64	Created rgen script and expanded available register types	ghutchis	7071d 13h	/
63	Added simple regression script. -r command runs all tests (serially), -c command checks results after all tests have completed.	ghutchis	7105d 18h	/
62	Reset timeout counter whenever a message is printed	ghutchis	7105d 18h	/

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Subversion Repositories tv80

[/] - Rev 81

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