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Rev Log message Author Age Path
86 Added old uploaded documents to new repository. root 5588d 16h /
85 Added old uploaded documents to new repository. root 5588d 22h /
84 New directory structure. root 5588d 22h /
83 Some fixes from Guy-- replace case with casex. hharte 5662d 04h /
82 Clean up spacing hharte 5672d 00h /
81 Initial version of TV80 Wishbone Wrapper hharte 5672d 01h /
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.
ghutchis 6771d 13h /
79 Added JR self-checking test ghutchis 6771d 13h /
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6814d 15h /
77 Added back files lost after server crash ghutchis 6846d 08h /
76 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6925d 15h /
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.
ghutchis 6925d 15h /
74 Changed default for T2Write to be 1, to match expected behavior for
most users.
ghutchis 6925d 16h /
73 Added RC4 encrypt/decrypt test ghutchis 6937d 10h /
72 Added copyright header ghutchis 6937d 10h /
71 Ported UART from T80 ghutchis 6998d 14h /
70 Added test for T16450 UART ghutchis 7049d 09h /
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7049d 09h /
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.
ghutchis 7057d 10h /
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.
ghutchis 7057d 10h /

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