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Rev Log message Author Age Path
95 Updated regression script to use SystemC simulation ghutchis 5350d 23h /
94 Ported over env_io.v from Verilog environment to tv_responder.
Basic tests from Verilog environment (hello, fib) now passing in
SystemC environment.
ghutchis 5353d 00h /
93 Added common header file for all systemc environment ghutchis 5353d 23h /
92 Added responder to top level, beginning of support for ihex load ghutchis 5358d 00h /
91 Preliminary support for SystemC/Verilator environment ghutchis 5358d 02h /
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.
ghutchis 5358d 02h /
89 RTL and environment fixes for nmi bug ghutchis 5378d 05h /
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5379d 20h /
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5395d 04h /
86 Added old uploaded documents to new repository. root 5618d 10h /
85 Added old uploaded documents to new repository. root 5618d 15h /
84 New directory structure. root 5618d 15h /
83 Some fixes from Guy-- replace case with casex. hharte 5691d 22h /
82 Clean up spacing hharte 5701d 18h /
81 Initial version of TV80 Wishbone Wrapper hharte 5701d 18h /
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.
ghutchis 6801d 06h /
79 Added JR self-checking test ghutchis 6801d 06h /
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6844d 08h /
77 Added back files lost after server crash ghutchis 6876d 02h /
76 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6955d 08h /

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