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Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
63	Synplicity was having troubles with the comment.	mohor	8227d 01h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8227d 23h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8228d 18h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8228d 22h	/
59	MSR register fixed.	mohor	8231d 19h	/
58	After reset modem status register MSR should be reset.	mohor	8231d 22h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8232d 22h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8232d 22h	/
55	some synthesis bugs fixed	gorban	8233d 10h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8233d 23h	/
53	Scratch register define added.	mohor	8235d 00h	/
52	Scratch register added	gorban	8235d 13h	/
51	Igor fixed break condition bugs	gorban	8235d 13h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8239d 18h	/
49	committed the debug interface file	gorban	8241d 11h	/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8242d 11h	/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8247d 13h	/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8248d 10h	/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8249d 11h	/
44	fixed more typo bugs	gorban	8263d 11h	/

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Subversion Repositories uart16550

[/] - Rev 63

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