URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8249d 10h	/
68	lsr[7] was not showing overrun errors.	mohor	8252d 17h	/
67	Missing declaration of rf_push_q fixed.	mohor	8259d 17h	/
66	rx push changed to be only one cycle wide.	mohor	8259d 17h	/
65	Warnings fixed (unused signals removed).	mohor	8260d 22h	/
64	Warnings cleared.	mohor	8260d 22h	/
63	Synplicity was having troubles with the comment.	mohor	8260d 23h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8261d 21h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8262d 16h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8262d 20h	/
59	MSR register fixed.	mohor	8265d 17h	/
58	After reset modem status register MSR should be reset.	mohor	8265d 20h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8266d 20h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8266d 20h	/
55	some synthesis bugs fixed	gorban	8267d 08h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8267d 21h	/
53	Scratch register define added.	mohor	8268d 21h	/
52	Scratch register added	gorban	8269d 10h	/
51	Igor fixed break condition bugs	gorban	8269d 10h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8273d 15h	/

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Subversion Repositories uart16550

[/] - Rev 69

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