URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] - Rev 69

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8225d 18h	/
68	lsr[7] was not showing overrun errors.	mohor	8229d 01h	/
67	Missing declaration of rf_push_q fixed.	mohor	8236d 01h	/
66	rx push changed to be only one cycle wide.	mohor	8236d 01h	/
65	Warnings fixed (unused signals removed).	mohor	8237d 06h	/
64	Warnings cleared.	mohor	8237d 07h	/
63	Synplicity was having troubles with the comment.	mohor	8237d 07h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8238d 06h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8239d 00h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8239d 04h	/
59	MSR register fixed.	mohor	8242d 01h	/
58	After reset modem status register MSR should be reset.	mohor	8242d 05h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8243d 04h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8243d 05h	/
55	some synthesis bugs fixed	gorban	8243d 16h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8244d 06h	/
53	Scratch register define added.	mohor	8245d 06h	/
52	Scratch register added	gorban	8245d 19h	/
51	Igor fixed break condition bugs	gorban	8245d 19h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8250d 00h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories uart16550

[/] - Rev 69

Filtering Options