URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8174d 17h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8188d 01h	/
71	Removed confusing comment	gorban	8199d 13h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8204d 22h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8213d 13h	/
68	lsr[7] was not showing overrun errors.	mohor	8216d 20h	/
67	Missing declaration of rf_push_q fixed.	mohor	8223d 20h	/
66	rx push changed to be only one cycle wide.	mohor	8223d 20h	/
65	Warnings fixed (unused signals removed).	mohor	8225d 01h	/
64	Warnings cleared.	mohor	8225d 02h	/
63	Synplicity was having troubles with the comment.	mohor	8225d 02h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8226d 01h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8226d 19h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8226d 23h	/
59	MSR register fixed.	mohor	8229d 20h	/
58	After reset modem status register MSR should be reset.	mohor	8229d 23h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8230d 23h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8230d 23h	/
55	some synthesis bugs fixed	gorban	8231d 11h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8232d 01h	/

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Subversion Repositories uart16550

[/] - Rev 73

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