URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8217d 01h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8230d 09h	/
71	Removed confusing comment	gorban	8241d 21h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8247d 06h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8255d 21h	/
68	lsr[7] was not showing overrun errors.	mohor	8259d 04h	/
67	Missing declaration of rf_push_q fixed.	mohor	8266d 04h	/
66	rx push changed to be only one cycle wide.	mohor	8266d 04h	/
65	Warnings fixed (unused signals removed).	mohor	8267d 09h	/
64	Warnings cleared.	mohor	8267d 10h	/
63	Synplicity was having troubles with the comment.	mohor	8267d 10h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8268d 09h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8269d 03h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8269d 07h	/
59	MSR register fixed.	mohor	8272d 04h	/
58	After reset modem status register MSR should be reset.	mohor	8272d 08h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8273d 07h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8273d 08h	/
55	some synthesis bugs fixed	gorban	8273d 19h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8274d 09h	/

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Subversion Repositories uart16550

[/] - Rev 73

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