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Rev	Log message	Author	Age	Path
97	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7379d 12h	/
96	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.	tadejm	7379d 12h	/
95	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.	tadejm	7379d 12h	/
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7379d 12h	/
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7379d 12h	/
92	This is revision 1.4, revision 1.5 was put there by mistake.	simons	7493d 05h	/
91	Removed files due to new complete testbench.	tadejm	7493d 20h	/
90	Add Flextronics header	avisha	7496d 03h	/
89	adjusted comment + define	dries	7576d 09h	/
88	added clearing the receiver fifo statuses on resets	gorban	7638d 22h	/
87	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.	gorban	7669d 00h	/
86	restored include for uart_defines.v in uart_test.v	gorban	7939d 04h	/
85	Updated documentation to include latest changes.	gorban	7972d 20h	/
84	The uart_defines.v file is included again in sources.	gorban	7985d 19h	/
83	Reverted to include uart_defines.v file in other files again.	gorban	7985d 19h	/
82	Updated to work with latest core.	gorban	7992d 17h	/
81	Added lastest additions.	gorban	7992d 17h	/
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7992d 17h	/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7992d 17h	/
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8145d 23h	/

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