OpenCores
URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] - Rev 11

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
11 UART16750: Removed dependency from std_logic_unsigned hasw 5625d 01h /
10 UART16750: Removed dependency from std_logic_unsigned hasw 5625d 01h /
9 Registered control line outputs hasw 5634d 03h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5634d 03h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5635d 07h /
6 THR empty interrupt register connected to RST hasw 5635d 08h /
5 Removed old component hasw 5636d 02h /
4 Removed swap file hasw 5636d 03h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5636d 03h /
2 Imported sources hasw 5636d 03h /
1 Standard project directories initialized by cvs2svn. 5636d 03h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.