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Rev Log message Author Age Path
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5599d 04h /
13 UART16750: Added automatic flow control hasw 5612d 05h /
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5612d 05h /
11 UART16750: Removed dependency from std_logic_unsigned hasw 5612d 05h /
10 UART16750: Removed dependency from std_logic_unsigned hasw 5612d 05h /
9 Registered control line outputs hasw 5621d 07h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5621d 07h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5622d 11h /
6 THR empty interrupt register connected to RST hasw 5622d 12h /
5 Removed old component hasw 5623d 06h /
4 Removed swap file hasw 5623d 07h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5623d 08h /
2 Imported sources hasw 5623d 08h /
1 Standard project directories initialized by cvs2svn. 5623d 08h /

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