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Rev Log message Author Age Path
21 Updated simulation files hasw 5443d 00h /
20 UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state hasw 5572d 22h /
19 Added old uploaded documents to new repository. root 5589d 03h /
18 Added old uploaded documents to new repository. root 5589d 08h /
17 New directory structure. root 5589d 08h /
16 UART16750: Added example project hasw 5609d 19h /
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5618d 22h /
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5620d 00h /
13 UART16750: Added automatic flow control hasw 5633d 01h /
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5633d 01h /
11 UART16750: Removed dependency from std_logic_unsigned hasw 5633d 01h /
10 UART16750: Removed dependency from std_logic_unsigned hasw 5633d 01h /
9 Registered control line outputs hasw 5642d 03h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5642d 03h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5643d 07h /
6 THR empty interrupt register connected to RST hasw 5643d 08h /
5 Removed old component hasw 5644d 02h /
4 Removed swap file hasw 5644d 03h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5644d 04h /
2 Imported sources hasw 5644d 04h /

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