URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] - Rev 21

Rev	Log message	Author	Age	Path
21	Updated simulation files	hasw	5438d 22h	/
20	UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state	hasw	5568d 20h	/
19	Added old uploaded documents to new repository.	root	5585d 00h	/
18	Added old uploaded documents to new repository.	root	5585d 06h	/
17	New directory structure.	root	5585d 06h	/
16	UART16750: Added example project	hasw	5605d 17h	/
15	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5614d 20h	/
14	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5615d 22h	/
13	UART16750: Added automatic flow control	hasw	5628d 22h	/
12	UART16750: Updated stimuli script with automatic flow control tests	hasw	5628d 22h	/
11	UART16750: Removed dependency from std_logic_unsigned	hasw	5628d 23h	/
10	UART16750: Removed dependency from std_logic_unsigned	hasw	5628d 23h	/
9	Registered control line outputs	hasw	5638d 00h	/
8	Make memory read in generic FIFO model synchronous for optimized used with XST	hasw	5638d 00h	/
7	Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST	hasw	5639d 05h	/
6	THR empty interrupt register connected to RST	hasw	5639d 06h	/
5	Removed old component	hasw	5640d 00h	/
4	Removed swap file	hasw	5640d 01h	/
3	This commit was manufactured by cvs2svn to create tag 'Import'.		5640d 01h	/
2	Imported sources	hasw	5640d 01h	/