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Rev Log message Author Age Path
9 Registered control line outputs hasw 5620d 00h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5620d 00h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5621d 04h /
6 THR empty interrupt register connected to RST hasw 5621d 05h /
5 Removed old component hasw 5621d 23h /
4 Removed swap file hasw 5622d 00h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5622d 00h /
2 Imported sources hasw 5622d 00h /
1 Standard project directories initialized by cvs2svn. 5622d 00h /

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