OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] - Rev 16

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
16 Adding testbench for wishbone slave module leonardoaraujo.santos 4436d 23h /
15 Taking out some warnings and transparent latches from the design leonardoaraujo.santos 4437d 00h /
14 Fixing some warnings... Adding wishbone slave leonardoaraujo.santos 4437d 20h /
13 Working on uart_control testbench... also applying some fixes... leonardoaraujo.santos 4437d 21h /
12 Working on the communication blocks leonardoaraujo.santos 4437d 22h /
11 Adding uart_communication_block leonardoaraujo.santos 4438d 00h /
10 Working on the control unit part leonardoaraujo.santos 4438d 04h /
9 Adding Control unit for uart block leonardoaraujo.santos 4438d 16h /
8 Solving some bugs in baud_generator.vhd leonardoaraujo.santos 4439d 02h /
7 Remember to clean project files leonardoaraujo.santos 4439d 23h /
6 Adding baud generator leonardoaraujo.santos 4439d 23h /
5 Adding sequential division (32 cycles per 32 bit word) leonardoaraujo.santos 4445d 00h /
4 Working on receiver leonardoaraujo.santos 4447d 01h /
3 Deleting unused files and changing tests leonardoaraujo.santos 4447d 01h /
2 Starting here .... leonardoaraujo.santos 4447d 03h /
1 The project and the structure was created root 4447d 18h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.