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Rev Log message Author Age Path
20 Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code... leonardoaraujo.santos 4437d 10h /
19 Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd) leonardoaraujo.santos 4437d 11h /
18 sdsd leonardoaraujo.santos 4437d 17h /
17 Working on slave testbench and fixing some bugs leonardoaraujo.santos 4437d 19h /
16 Adding testbench for wishbone slave module leonardoaraujo.santos 4437d 19h /
15 Taking out some warnings and transparent latches from the design leonardoaraujo.santos 4437d 20h /
14 Fixing some warnings... Adding wishbone slave leonardoaraujo.santos 4438d 16h /
13 Working on uart_control testbench... also applying some fixes... leonardoaraujo.santos 4438d 17h /
12 Working on the communication blocks leonardoaraujo.santos 4438d 18h /
11 Adding uart_communication_block leonardoaraujo.santos 4438d 20h /
10 Working on the control unit part leonardoaraujo.santos 4439d 00h /
9 Adding Control unit for uart block leonardoaraujo.santos 4439d 12h /
8 Solving some bugs in baud_generator.vhd leonardoaraujo.santos 4439d 22h /
7 Remember to clean project files leonardoaraujo.santos 4440d 19h /
6 Adding baud generator leonardoaraujo.santos 4440d 19h /
5 Adding sequential division (32 cycles per 32 bit word) leonardoaraujo.santos 4445d 21h /
4 Working on receiver leonardoaraujo.santos 4447d 21h /
3 Deleting unused files and changing tests leonardoaraujo.santos 4447d 21h /
2 Starting here .... leonardoaraujo.santos 4447d 23h /
1 The project and the structure was created root 4448d 14h /

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