URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] - Rev 21

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Rev	Log message	Author	Age	Path
21	Preparing to rewrite uart_control, adding pin to indicate data available at the RX	leonardoaraujo.santos	4407d 14h	/
20	Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code...	leonardoaraujo.santos	4407d 21h	/
19	Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd)	leonardoaraujo.santos	4407d 22h	/
18	sdsd	leonardoaraujo.santos	4408d 05h	/
17	Working on slave testbench and fixing some bugs	leonardoaraujo.santos	4408d 06h	/
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4408d 06h	/
15	Taking out some warnings and transparent latches from the design	leonardoaraujo.santos	4408d 08h	/
14	Fixing some warnings... Adding wishbone slave	leonardoaraujo.santos	4409d 03h	/
13	Working on uart_control testbench... also applying some fixes...	leonardoaraujo.santos	4409d 04h	/
12	Working on the communication blocks	leonardoaraujo.santos	4409d 05h	/
11	Adding uart_communication_block	leonardoaraujo.santos	4409d 08h	/
10	Working on the control unit part	leonardoaraujo.santos	4409d 12h	/
9	Adding Control unit for uart block	leonardoaraujo.santos	4409d 23h	/
8	Solving some bugs in baud_generator.vhd	leonardoaraujo.santos	4410d 10h	/
7	Remember to clean project files	leonardoaraujo.santos	4411d 06h	/
6	Adding baud generator	leonardoaraujo.santos	4411d 06h	/
5	Adding sequential division (32 cycles per 32 bit word)	leonardoaraujo.santos	4416d 08h	/
4	Working on receiver	leonardoaraujo.santos	4418d 08h	/
3	Deleting unused files and changing tests	leonardoaraujo.santos	4418d 09h	/
2	Starting here ....	leonardoaraujo.santos	4418d 10h	/

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Subversion Repositories uart_block

[/] - Rev 21

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