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Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4937d 08h /
25 added sync FIFO unneback 4937d 21h /
24 added vl_dff_ce_set unneback 4939d 05h /
23 fixed port map error in async fifo 1r1w unneback 4939d 20h /
22 added binary counters unneback 4940d 01h /
21 reg -> wire in and or mux in logic unneback 4940d 21h /
20 naming convention vl_ unneback 4942d 08h /
19 naming convention vl_ unneback 4942d 08h /
18 naming convention vl_ unneback 4942d 08h /
17 unneback 5005d 22h /
16 converting utility for ROM unneback 5006d 09h /
15 added delay line unneback 5012d 05h /
14 reg -> wire for various signals unneback 5012d 11h /
13 cosmetic update unneback 5012d 12h /
12 added wishbone comliant modules unneback 5013d 08h /
11 async fifo simplex unneback 5013d 23h /
10 added dff_ce_clear unneback 5015d 22h /
9 added dff_ce_clear unneback 5015d 22h /
8 added dff_ce_clear unneback 5015d 22h /
7 mem update unneback 5015d 23h /

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