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Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4942d 13h /
25 added sync FIFO unneback 4943d 02h /
24 added vl_dff_ce_set unneback 4944d 10h /
23 fixed port map error in async fifo 1r1w unneback 4945d 01h /
22 added binary counters unneback 4945d 06h /
21 reg -> wire in and or mux in logic unneback 4946d 02h /
20 naming convention vl_ unneback 4947d 13h /
19 naming convention vl_ unneback 4947d 13h /
18 naming convention vl_ unneback 4947d 13h /
17 unneback 5011d 03h /
16 converting utility for ROM unneback 5011d 14h /
15 added delay line unneback 5017d 10h /
14 reg -> wire for various signals unneback 5017d 15h /
13 cosmetic update unneback 5017d 17h /
12 added wishbone comliant modules unneback 5018d 13h /
11 async fifo simplex unneback 5019d 04h /
10 added dff_ce_clear unneback 5021d 03h /
9 added dff_ce_clear unneback 5021d 03h /
8 added dff_ce_clear unneback 5021d 03h /
7 mem update unneback 5021d 04h /

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