URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 14

Rev	Log message	Author	Age	Path
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5366d 23h	/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5367d 02h	/
12	Minor update of whishbone FSMs in TB	mikaeljf	5377d 02h	/
11	Initial version with support for DDR	mikaeljf	5377d 14h	/
10		unneback	5404d 22h	/
9	testbench	unneback	5404d 22h	/
8		unneback	5500d 18h	/
7		unneback	5500d 18h	/
6		unneback	5500d 19h	/
5	pass initial testing	unneback	5500d 19h	/
4		unneback	5501d 22h	/
3		unneback	5502d 01h	/
2	initial	unneback	5507d 23h	/
1	The project was created and the structure was created	root	5507d 23h	/