URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 23

Rev	Log message	Author	Age	Path
23	Removed redundant code.	mikaeljf	5279d 20h	/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5281d 15h	/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5285d 19h	/
20	Minor update of sdc-file.	mikaeljf	5287d 20h	/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5294d 01h	/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5294d 22h	/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5297d 20h	/
16	Added fizzim.pl	mikaeljf	5297d 21h	/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5298d 21h	/
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5388d 23h	/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5389d 02h	/
12	Minor update of whishbone FSMs in TB	mikaeljf	5399d 03h	/
11	Initial version with support for DDR	mikaeljf	5399d 15h	/
10		unneback	5426d 23h	/
9	testbench	unneback	5426d 23h	/
8		unneback	5522d 19h	/
7		unneback	5522d 19h	/
6		unneback	5522d 19h	/
5	pass initial testing	unneback	5522d 20h	/
4		unneback	5523d 23h	/