URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 43

Rev	Log message	Author	Age	Path
43		unneback	5255d 16h	/
42	added pipeline stage for egress FIFO readot	unneback	5256d 00h	/
41	Added two alternate data capture functions.	mikaeljf	5256d 07h	/
40	updated fifo interfaces with re/rd and we/wr	unneback	5256d 14h	/
39	updated FIFO and SDR 16	unneback	5257d 02h	/
38	casex in rw state to save logic	unneback	5259d 09h	/
37		unneback	5260d 00h	/
36		unneback	5260d 00h	/
35	work for limited test case	unneback	5260d 08h	/
34	added	unneback	5260d 08h	/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5260d 10h	/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5263d 14h	/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5265d 07h	/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5265d 07h	/
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5269d 07h	/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5269d 09h	/
27		unneback	5273d 01h	/
26	compiles OK, not simulated	unneback	5275d 00h	/
25		unneback	5275d 03h	/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5275d 14h	/