URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 85

Rev	Log message	Author	Age	Path
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5129d 05h	/
84		mikaeljf	5133d 04h	/
83		mikaeljf	5133d 23h	/
82		mikaeljf	5134d 04h	/
81		mikaeljf	5135d 00h	/
80		mikaeljf	5135d 01h	/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5172d 15h	/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5174d 22h	/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5182d 21h	/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5187d 21h	/
75		mikaeljf	5187d 23h	/
74	Minor update of rtl Makefile.	mikaeljf	5191d 22h	/
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5191d 23h	/
72	Restored lost revisions 69 and 70.	mikaeljf	5191d 23h	/
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5192d 00h	/
70		mikaeljf	5195d 06h	/
69		mikaeljf	5196d 03h	/
68	cleaqnup	unneback	5197d 15h	/
67	added FSM for wb if	unneback	5197d 15h	/
66		unneback	5197d 18h	/