URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] - Rev 16

Rev	Log message	Author	Age	Path
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8347d 06h	/
15	Created directory structure (documentation, vhdl, verilog)	rherveille	8382d 20h	/
14	Added CLUT bank switching. Replaced multiplier with simple counters. Fixed timing bug.	rherveille	8383d 15h	/
13	Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore.	rherveille	8384d 03h	/
12	Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd); adds color-lookup-table to the VGA core (i.e. on-chip CLUT). Ram generation has been tested with Altera and Xilinx parts.	rherveille	8393d 07h	/
11	Major bug fixes in Wishbone Master and ColorProcessor blocks. Core did not respond correctly to delayed ACK_I signals. Added built-in Color Lookup Tables.	rherveille	8393d 07h	/
10	Design now uses Xilinx-BlockRAMs instead of selectRAM	rherveille	8399d 22h	/
9	no message	rherveille	8400d 16h	/
8	Revised core. Removed unused signals	rherveille	8406d 00h	/
7	revised counter.vhd	rherveille	8410d 02h	/
6	no message	rherveille	8411d 01h	/
5	Fixed a bug in wishbone master. Updated simulation files also	rherveille	8415d 01h	/
4	changed wishbone address sections.	rherveille	8426d 02h	/
3	This commit was manufactured by cvs2svn to create tag 'beta'.		8439d 06h	/
2	initial release	rherveille	8439d 06h	/
1	Standard project directories initialized by cvs2svn.		8439d 06h	/