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Rev Log message Author Age Path
32 Fixed dat_o incomplete sensitivity list. rherveille 8158d 14h /
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8167d 10h /
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8176d 15h /
29 Added wb_ack delay section to testbench rherveille 8176d 15h /
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8186d 17h /
27 Added 32bpp
Fixed some typos
Added bandwidth section		 rherveille 8186d 17h /
26 Added 32bpp tests rherveille 8186d 17h /
25 C-include file.
Initial release		 rherveille 8253d 10h /
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8260d 13h /
23 Added Copyright/Licence header rherveille 8261d 09h /
22 VGA Core v2.0
Document revision 0.7		 rherveille 8281d 06h /
21 VGA Core v2.0
Document revision 0.7		 rherveille 8281d 06h /
20 Switched parameter order. rherveille 8290d 10h /
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8290d 11h /
18 Removed files. They are not used anymore. rherveille 8319d 09h /
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8319d 09h /
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8346d 15h /
15 Created directory structure (documentation, vhdl, verilog) rherveille 8382d 05h /
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8383d 00h /
13 Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore. rherveille 8383d 12h /

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