OpenCores
URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] - Rev 33

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8160d 20h /
32 Fixed dat_o incomplete sensitivity list. rherveille 8168d 01h /
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8176d 20h /
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8186d 01h /
29 Added wb_ack delay section to testbench rherveille 8186d 01h /
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8196d 03h /
27 Added 32bpp
Fixed some typos
Added bandwidth section		 rherveille 8196d 03h /
26 Added 32bpp tests rherveille 8196d 03h /
25 C-include file.
Initial release		 rherveille 8262d 21h /
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8270d 00h /
23 Added Copyright/Licence header rherveille 8270d 19h /
22 VGA Core v2.0
Document revision 0.7		 rherveille 8290d 16h /
21 VGA Core v2.0
Document revision 0.7		 rherveille 8290d 16h /
20 Switched parameter order. rherveille 8299d 21h /
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8299d 22h /
18 Removed files. They are not used anymore. rherveille 8328d 19h /
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8328d 19h /
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8356d 01h /
15 Created directory structure (documentation, vhdl, verilog) rherveille 8391d 15h /
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8392d 10h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.