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Rev Log message Author Age Path
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7736d 20h /
46 Added WISHBONE revB.3 sanity checks rherveille 7736d 20h /
45 Changed timing generator; made it smaller and easier. rherveille 7737d 01h /
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7737d 01h /
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7737d 16h /
42 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8070d 02h /
41 specs version 1.1 rherveille 8070d 02h /
40 no message rherveille 8070d 02h /
39 Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).		 rherveille 8070d 03h /
38 Changed testbench to reflect modified VGA timing generator. rherveille 8070d 03h /
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8085d 07h /
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8093d 08h /
35 no message rherveille 8093d 12h /
34 Added hardware cursor support to wishbone master.
Added provision to turn-off 3D cursors.
Fixed some minor bugs.		 rherveille 8116d 21h /
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8117d 02h /
32 Fixed dat_o incomplete sensitivity list. rherveille 8124d 07h /
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8133d 03h /
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8142d 08h /
29 Added wb_ack delay section to testbench rherveille 8142d 08h /
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8152d 10h /

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