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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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Rev Log message Author Age Path
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3095d 11h /
23 Fixed reset of application registers fransschreuder 3152d 16h /
22 Added dma_soft_reset to trigger register resets fransschreuder 3158d 16h /
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3167d 13h /
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3181d 12h /
19 * driver/README updated oussamak 3187d 14h /
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3187d 15h /
17 Changed name of toplevel, to make tree consistent oussamak 3201d 18h /
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3251d 12h /
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3251d 12h /
14 RENAMED:
-- simulation folder		 aborga 3251d 14h /
13 RENAMED:
-- script		 aborga 3251d 14h /
12 Fixed http://opencores.org/bug,view,2524 fransschreuder 3326d 14h /
11 MODIFIED:
-- updated documentation		 aborga 3339d 11h /
10 Changed:
LOC => Package_pin		 fransschreuder 3349d 12h /
9 Added actual version information (Build date and svn revision) in BOARD_ID register fransschreuder 3378d 10h /
8 Changed:
* Added support for circular DMA (wrap around)
* Fixed Read / Write interrupts		 fransschreuder 3378d 16h /
7 Changed:
* Simplified address calculation to relax timing
* Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing
* Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk
* Added support for the High tech Global HTG710 board		 fransschreuder 3418d 12h /
6 Changed:
* fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable
* Fixed missing signals in sensitivity list		 fransschreuder 3424d 10h /
5 Changed:
* Added two registers to test interrupts vectors 2 and 3
* Added a register to read generic constants to show number of interrupts / number of descriptors
* fixed consistency of generic default values among different design units
* fixed route of pll_locked / register map record, to allow non-flattening of synthesis		 fransschreuder 3425d 14h /

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