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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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Rev Log message Author Age Path
28 Added registermap reset fransschreuder 3094d 07h /
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3094d 10h /
26 Added sys_clk constraint fransschreuder 3094d 12h /
25 Added scripts and constraints for KCU105 fransschreuder 3094d 13h /
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3095d 06h /
23 Fixed reset of application registers fransschreuder 3152d 12h /
22 Added dma_soft_reset to trigger register resets fransschreuder 3158d 11h /
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3167d 09h /
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3181d 07h /
19 * driver/README updated oussamak 3187d 09h /
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3187d 11h /
17 Changed name of toplevel, to make tree consistent oussamak 3201d 13h /
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3251d 07h /
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3251d 08h /
14 RENAMED:
-- simulation folder		 aborga 3251d 09h /
13 RENAMED:
-- script		 aborga 3251d 09h /
12 Fixed http://opencores.org/bug,view,2524 fransschreuder 3326d 09h /
11 MODIFIED:
-- updated documentation		 aborga 3339d 07h /
10 Changed:
LOC => Package_pin		 fransschreuder 3349d 07h /
9 Added actual version information (Build date and svn revision) in BOARD_ID register fransschreuder 3378d 05h /

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