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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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Rev Log message Author Age Path
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 2952d 02h /
31 Added example application documentation. oussamak 3046d 04h /
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3046d 04h /
29 Improved application to reflect both up and down transfers fransschreuder 3088d 02h /
28 Added registermap reset fransschreuder 3088d 04h /
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3088d 07h /
26 Added sys_clk constraint fransschreuder 3088d 10h /
25 Added scripts and constraints for KCU105 fransschreuder 3088d 10h /
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3089d 03h /
23 Fixed reset of application registers fransschreuder 3146d 09h /
22 Added dma_soft_reset to trigger register resets fransschreuder 3152d 08h /
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3161d 06h /
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3175d 04h /
19 * driver/README updated oussamak 3181d 06h /
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3181d 08h /
17 Changed name of toplevel, to make tree consistent oussamak 3195d 11h /
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3245d 05h /
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3245d 05h /
14 RENAMED:
-- simulation folder		 aborga 3245d 06h /
13 RENAMED:
-- script		 aborga 3245d 06h /

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