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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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39 Added Wishbone bus to Wupper plus a Wishbone memory as an example. broel 2403d 03h /
38 Fixed include of stdint.h broel 2411d 10h /
37 * Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen		 fransschreuder 2412d 02h /
36 Updated documentation fransschreuder 2747d 03h /
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup		 fransschreuder 2801d 08h /
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards		 fransschreuder 2907d 03h /
33 ADDED:
-- supportedtools.tex, again to test the OC repo		 aborga 2952d 01h /
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 2952d 02h /
31 Added example application documentation. oussamak 3046d 03h /
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3046d 04h /
29 Improved application to reflect both up and down transfers fransschreuder 3088d 02h /
28 Added registermap reset fransschreuder 3088d 04h /
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3088d 07h /
26 Added sys_clk constraint fransschreuder 3088d 09h /
25 Added scripts and constraints for KCU105 fransschreuder 3088d 09h /
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3089d 03h /
23 Fixed reset of application registers fransschreuder 3146d 08h /
22 Added dma_soft_reset to trigger register resets fransschreuder 3152d 08h /
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3161d 05h /
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3175d 04h /

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