URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] - Rev 15

Rev	Log message	Author	Age	Path
15	Quick update, making this module verilatable again	dgisselq	2280d 08h	/
14	Added a reset line upon user request	dgisselq	2280d 08h	/
13	Bug fix release--fixes the bugs Antti pointed out.	dgisselq	2292d 21h	/
12	Added Verilators obj_dir to the list of ignored files	dgisselq	2390d 09h	/
11	Updated the bench/formal properties SVN will now ignore the build files associated with this directory: .smt2, .yslog, *.vcd	dgisselq	2390d 09h	/
10	Added files to flush out the formal proof capability	dgisselq	2390d 09h	/
9	Added a formal directory	dgisselq	2390d 09h	/
8	The WB to AXI translator wrks and works well. A proof of this will be added shortly.	dgisselq	2390d 09h	/
7	Simplified.	dgisselq	2707d 09h	/
6	IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet)	dgisselq	2835d 05h	/
5	Adjusted variable names to match the spec and the MIG.	dgisselq	2839d 20h	/
4	Adjusted the core quickly so it should work for 128-bit wide wishbone busses as well as 32-bit wide busses.	dgisselq	2840d 02h	/
3	Fixed the Verilator compile-time bugs. Still haven't tested the core.	dgisselq	2840d 02h	/
2	Initial check in. Core not (yet) tested, verified, or validated.	dgisselq	2840d 02h	/
1	The project and the structure was created	root	2840d 03h	/