OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] - Rev 47

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5330d 15h /
46 Update to remove stack registers and add new register text. rehayes 5362d 13h /
45 Update to remove stack registers and add new register text. rehayes 5362d 13h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5364d 12h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5364d 12h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5364d 12h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5365d 14h /
40 Update for single program counter adder rehayes 5385d 17h /
39 delete rehayes 5393d 18h /
38 Nov 9 2009 update notes rehayes 5393d 19h /
37 RAM model breakout for testbench rehayes 5393d 19h /
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5393d 19h /
35 Add byte lane select input to all tasks rehayes 5393d 19h /
34 minor changes related to wishbone master interface rehayes 5393d 19h /
33 Update with some new pin information rehayes 5393d 19h /
32 added ram block rehayes 5393d 20h /
31 Cleanup for MAX_CHANNEL bus rehayes 5405d 14h /
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5405d 14h /
29 Added some constant assigments, still needs more work to complete rehayes 5405d 14h /
28 Added comment line rehayes 5405d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.