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Rev Log message Author Age Path
49 First pass with instruction set details rehayes 5425d 18h /
48 Update for SBC ana ADC condition code changes rehayes 5425d 18h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5425d 19h /
46 Update to remove stack registers and add new register text. rehayes 5457d 17h /
45 Update to remove stack registers and add new register text. rehayes 5457d 17h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5459d 15h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5459d 16h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5459d 16h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5460d 18h /
40 Update for single program counter adder rehayes 5480d 21h /
39 delete rehayes 5488d 22h /
38 Nov 9 2009 update notes rehayes 5488d 22h /
37 RAM model breakout for testbench rehayes 5488d 23h /
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5488d 23h /
35 Add byte lane select input to all tasks rehayes 5488d 23h /
34 minor changes related to wishbone master interface rehayes 5488d 23h /
33 Update with some new pin information rehayes 5488d 23h /
32 added ram block rehayes 5488d 23h /
31 Cleanup for MAX_CHANNEL bus rehayes 5500d 18h /
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5500d 18h /

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