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Rev Log message Author Age Path
55 Minor change to instruction set details. rehayes 5272d 12h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5272d 12h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5272d 12h /
52 Minor changes to aide waveform debug rehayes 5272d 12h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5288d 09h /
50 incremental update to match status bit changes rehayes 5288d 09h /
49 First pass with instruction set details rehayes 5288d 09h /
48 Update for SBC ana ADC condition code changes rehayes 5288d 09h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5288d 09h /
46 Update to remove stack registers and add new register text. rehayes 5320d 08h /
45 Update to remove stack registers and add new register text. rehayes 5320d 08h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5322d 06h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5322d 06h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5322d 07h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5323d 09h /
40 Update for single program counter adder rehayes 5343d 11h /
39 delete rehayes 5351d 12h /
38 Nov 9 2009 update notes rehayes 5351d 13h /
37 RAM model breakout for testbench rehayes 5351d 13h /
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5351d 13h /

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