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Rev Log message Author Age Path
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5251d 05h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5267d 06h /
55 Minor change to instruction set details. rehayes 5267d 06h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5267d 06h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5267d 06h /
52 Minor changes to aide waveform debug rehayes 5267d 06h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5283d 03h /
50 incremental update to match status bit changes rehayes 5283d 03h /
49 First pass with instruction set details rehayes 5283d 03h /
48 Update for SBC ana ADC condition code changes rehayes 5283d 03h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5283d 03h /
46 Update to remove stack registers and add new register text. rehayes 5315d 02h /
45 Update to remove stack registers and add new register text. rehayes 5315d 02h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5317d 00h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5317d 00h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5317d 01h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5318d 03h /
40 Update for single program counter adder rehayes 5338d 05h /
39 delete rehayes 5346d 06h /
38 Nov 9 2009 update notes rehayes 5346d 07h /

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