URL https://opencores.org/ocsvn/xgate/xgate/trunk

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Rev	Log message	Author	Age	Path
62	Cleanup implicit wire declarations.	rehayes	5189d 02h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5196d 01h	/
60	Add ability at insert wait states on RAM access	rehayes	5196d 01h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5196d 01h	/
58	WISHBONE Bus update.	rehayes	5248d 01h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5248d 04h	/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5264d 05h	/
55	Minor change to instruction set details.	rehayes	5264d 05h	/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5264d 05h	/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5264d 05h	/
52	Minor changes to aide waveform debug	rehayes	5264d 05h	/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5280d 01h	/
50	incremental update to match status bit changes	rehayes	5280d 01h	/
49	First pass with instruction set details	rehayes	5280d 02h	/
48	Update for SBC ana ADC condition code changes	rehayes	5280d 02h	/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5280d 02h	/
46	Update to remove stack registers and add new register text.	rehayes	5312d 00h	/
45	Update to remove stack registers and add new register text.	rehayes	5312d 00h	/
44	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5313d 23h	/
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5313d 23h	/

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Subversion Repositories xgate

[/] - Rev 62

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