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Rev Log message Author Age Path
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5159d 05h /
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5159d 05h /
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5179d 01h /
65 Parameterize delays based on number of RAM wait states. rehayes 5179d 01h /
64 Fixed more bugs related to wait states and debug mode. rehayes 5179d 01h /
63 Remove historical output ports that are no longer used. rehayes 5189d 00h /
62 Cleanup implicit wire declarations. rehayes 5189d 00h /
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5196d 00h /
60 Add ability at insert wait states on RAM access rehayes 5196d 00h /
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5196d 00h /
58 WISHBONE Bus update. rehayes 5248d 00h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5248d 03h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5264d 04h /
55 Minor change to instruction set details. rehayes 5264d 04h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5264d 04h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5264d 04h /
52 Minor changes to aide waveform debug rehayes 5264d 04h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5280d 00h /
50 incremental update to match status bit changes rehayes 5280d 00h /
49 First pass with instruction set details rehayes 5280d 01h /

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