OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] - Rev 68

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5237d 19h /
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5237d 19h /
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5257d 14h /
65 Parameterize delays based on number of RAM wait states. rehayes 5257d 14h /
64 Fixed more bugs related to wait states and debug mode. rehayes 5257d 15h /
63 Remove historical output ports that are no longer used. rehayes 5267d 14h /
62 Cleanup implicit wire declarations. rehayes 5267d 14h /
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5274d 14h /
60 Add ability at insert wait states on RAM access rehayes 5274d 14h /
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5274d 14h /
58 WISHBONE Bus update. rehayes 5326d 13h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5326d 17h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5342d 17h /
55 Minor change to instruction set details. rehayes 5342d 17h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5342d 17h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5342d 17h /
52 Minor changes to aide waveform debug rehayes 5342d 18h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5358d 14h /
50 incremental update to match status bit changes rehayes 5358d 14h /
49 First pass with instruction set details rehayes 5358d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.