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Rev	Log message	Author	Age	Path
73	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5167d 08h	/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5167d 08h	/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5168d 10h	/
70	Updated with interrupt bypass controll registers.	rehayes	5168d 10h	/
69	New test to verify irq interrupt priority encoder.	rehayes	5168d 11h	/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5168d 11h	/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5168d 11h	/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5188d 07h	/
65	Parameterize delays based on number of RAM wait states.	rehayes	5188d 07h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5188d 07h	/
63	Remove historical output ports that are no longer used.	rehayes	5198d 06h	/
62	Cleanup implicit wire declarations.	rehayes	5198d 06h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5205d 06h	/
60	Add ability at insert wait states on RAM access	rehayes	5205d 06h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5205d 06h	/
58	WISHBONE Bus update.	rehayes	5257d 06h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5257d 09h	/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5273d 09h	/
55	Minor change to instruction set details.	rehayes	5273d 09h	/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5273d 10h	/

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[/] - Rev 73

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