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Rev Log message Author Age Path
81 Initial checkin of the SKIPJACK encrypt/decrypt application program rehayes 5203d 19h /
80 Added IRQ bypass registers and Test bench appendix rehayes 5265d 20h /
79 Added IRQ bypass registers and Test bench appendix rehayes 5265d 20h /
78 Added IRQ bypass registers and Test bench appendix rehayes 5265d 20h /
77 Documentation update rehayes 5265d 20h /
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5288d 21h /
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5288d 21h /
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5293d 22h /
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5293d 22h /
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5293d 22h /
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5295d 01h /
70 Updated with interrupt bypass controll registers. rehayes 5295d 01h /
69 New test to verify irq interrupt priority encoder. rehayes 5295d 01h /
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5295d 01h /
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5295d 02h /
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5314d 21h /
65 Parameterize delays based on number of RAM wait states. rehayes 5314d 21h /
64 Fixed more bugs related to wait states and debug mode. rehayes 5314d 21h /
63 Remove historical output ports that are no longer used. rehayes 5324d 21h /
62 Cleanup implicit wire declarations. rehayes 5324d 21h /

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