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Rev Log message Author Age Path
86 Add JTAG test tasks rehayes 4931d 09h /
85 Corrections to instruction set details example code, added test bench debugger. rehayes 5205d 18h /
84 Added notes on SKIPJACK encrypt/decrypt applications, testbench debugger and user guide corrections. rehayes 5205d 18h /
83 Add subroutine quailifier. rehayes 5205d 18h /
82 Added debug module to assist in software debugging. rehayes 5206d 13h /
81 Initial checkin of the SKIPJACK encrypt/decrypt application program rehayes 5206d 13h /
80 Added IRQ bypass registers and Test bench appendix rehayes 5268d 14h /
79 Added IRQ bypass registers and Test bench appendix rehayes 5268d 14h /
78 Added IRQ bypass registers and Test bench appendix rehayes 5268d 14h /
77 Documentation update rehayes 5268d 14h /
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5291d 15h /
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5291d 15h /
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5296d 16h /
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5296d 16h /
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5296d 16h /
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5297d 19h /
70 Updated with interrupt bypass controll registers. rehayes 5297d 19h /
69 New test to verify irq interrupt priority encoder. rehayes 5297d 19h /
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5297d 20h /
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5297d 20h /

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