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Rev Log message Author Age Path
93 Initial revision, memory image for skipjack test. rehayes 4714d 17h /
92 Add sync reset to bypass register. rehayes 4714d 17h /
91 Update to use one ISR to handle all 127 interrupts. rehayes 4714d 17h /
90 Cosmetic omment changes. rehayes 4714d 17h /
89 Code cleanup. rehayes 4728d 16h /
88 Updated with complete code rehayes 4802d 01h /
87 First pass JTAG TAP, state machine working but needs work to complete reset of TAP. rehayes 4928d 15h /
86 Add JTAG test tasks rehayes 4928d 15h /
85 Corrections to instruction set details example code, added test bench debugger. rehayes 5203d 00h /
84 Added notes on SKIPJACK encrypt/decrypt applications, testbench debugger and user guide corrections. rehayes 5203d 00h /
83 Add subroutine quailifier. rehayes 5203d 00h /
82 Added debug module to assist in software debugging. rehayes 5203d 19h /
81 Initial checkin of the SKIPJACK encrypt/decrypt application program rehayes 5203d 19h /
80 Added IRQ bypass registers and Test bench appendix rehayes 5265d 20h /
79 Added IRQ bypass registers and Test bench appendix rehayes 5265d 20h /
78 Added IRQ bypass registers and Test bench appendix rehayes 5265d 20h /
77 Documentation update rehayes 5265d 20h /
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5288d 21h /
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5288d 21h /
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5293d 22h /

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