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Rev Log message Author Age Path
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4259d 02h /
20 Updates for Xilinx synthesis antanguay 4548d 20h /
19 Updates for 32/64 bit systems antanguay 4723d 21h /
18 Updates for linux 32-bit antanguay 4724d 18h /
17 Fixed deprecated SystemC warnings antanguay 4727d 02h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4727d 08h /
15 Updated for Verilator 3.813 antanguay 4746d 08h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5335d 03h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5335d 03h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5335d 04h /
11 Fixed clock crossing antanguay 5441d 01h /
10 Added details to spec antanguay 5538d 20h /
9 Added old uploaded documents to new repository. root 5613d 07h /
8 Added old uploaded documents to new repository. root 5613d 13h /
7 New directory structure. root 5613d 13h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5889d 21h /
5 Fixed compilation antanguay 5895d 21h /
4 Created antanguay 5895d 23h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 5896d 01h /
2 Initial revision antanguay 5896d 01h /

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