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Rev Log message Author Age Path
26 Fix packet count antanguay 4217d 09h /
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4217d 11h /
24 Use FIFO's for statistics clock domain crossing antanguay 4217d 12h /
23 Adding basic packet stats antanguay 4217d 18h /
22 Added prototype system verilog testbench antanguay 4219d 15h /
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4219d 15h /
20 Updates for Xilinx synthesis antanguay 4509d 09h /
19 Updates for 32/64 bit systems antanguay 4684d 11h /
18 Updates for linux 32-bit antanguay 4685d 07h /
17 Fixed deprecated SystemC warnings antanguay 4687d 15h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4687d 21h /
15 Updated for Verilator 3.813 antanguay 4706d 22h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5295d 16h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5295d 17h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5295d 17h /
11 Fixed clock crossing antanguay 5401d 14h /
10 Added details to spec antanguay 5499d 09h /
9 Added old uploaded documents to new repository. root 5573d 21h /
8 Added old uploaded documents to new repository. root 5574d 02h /
7 New directory structure. root 5574d 02h /

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