URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] - Rev 21

Rev	Log message	Author	Age	Path
21	Since all BRAM is unified in one component, this testbench is not necessary anymore.	lcdsgmtr	3226d 09h	/
20	Update RAM package to allow for 15-bit address. Update test bench to use address width parameter.	lcdsgmtr	3226d 09h	/
19	Makefile for building memory block testbench.	lcdsgmtr	3226d 09h	/
18	Ignore work files from GHDL.	lcdsgmtr	3226d 09h	/
17	Moving the generic block ram component piece by piece to a better implementation.	lcdsgmtr	3226d 09h	/
16	Re-write of memory in function of initial array memory blocks.	lcdsgmtr	3226d 09h	/
15	Unification of all RAM parts into one interface.	lcdsgmtr	3226d 09h	/
14	Simple implementation project.	lcdsgmtr	3358d 08h	/
13	Updated smallest Xilinx configuration.	lcdsgmtr	3358d 08h	/
12	Update Xilinx configurations.	lcdsgmtr	3358d 08h	/
11	Successful run of the simulation. Correct results.	lcdsgmtr	3358d 10h	/
10	Correct build with GHDL.	lcdsgmtr	3358d 10h	/
9	This makes sure that this GHDL configuration analyses correctly.	lcdsgmtr	3358d 10h	/
8	Rebuilding the configuration to build the first system using GHDL.	lcdsgmtr	3359d 08h	/
7	Moved package for initialising memory also to src.	lcdsgmtr	3359d 08h	/
6	Removed some unnecessary files and directories. Moved other files to new directories.	lcdsgmtr	3359d 08h	/
5	Re-organisation of repository.	lcdsgmtr	3360d 10h	/
4	Added directories for guiding implementation using Xilinx ISE and GHDL.	lcdsgmtr	3395d 10h	/
3	Added Makefile for GHDL.	lcdsgmtr	3480d 08h	/
2	First checkin to make sure that the project does not get stale.	lcdsgmtr	3482d 11h	/