| Rev |
Log message |
Author |
Age |
Path |
| 25 |
Fixing compile time warnings. |
dgisselq |
3044d 04h |
/ |
| 24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
3050d 02h |
/ |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3052d 13h |
/ |
| 22 |
Added the mkdatev.pl file. (Oops!) |
dgisselq |
3055d 06h |
/ |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3105d 13h |
/ |
| 20 |
Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board. |
dgisselq |
3105d 13h |
/ |
| 19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3105d 13h |
/ |
| 18 |
Got the bitfile back up to speed at 80 MHz. |
dgisselq |
3109d 03h |
/ |
| 17 |
Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...) |
dgisselq |
3109d 03h |
/ |
| 16 |
Updates to allow a test of the ICAP configuration interface. |
dgisselq |
3109d 03h |
/ |
| 15 |
WORKING VERSION! ... or, at least the memory test works. |
dgisselq |
3110d 23h |
/ |
| 14 |
Quick bug fix. |
dgisselq |
3110d 23h |
/ |
| 13 |
This version is now working. (It probably would've worked before, but
everything is now working.) |
dgisselq |
3110d 23h |
/ |
| 12 |
Modified to match the settings I'm now using within ISE. |
dgisselq |
3111d 02h |
/ |
| 11 |
Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.) |
dgisselq |
3111d 02h |
/ |
| 10 |
Changed the name of the memtest.s file. |
dgisselq |
3111d 02h |
/ |
| 9 |
Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz. |
dgisselq |
3111d 02h |
/ |
| 8 |
Added an interface description to the comments at the top of the file. |
dgisselq |
3113d 11h |
/ |
| 7 |
Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault. |
dgisselq |
3113d 12h |
/ |
| 6 |
Initial file load, likely to be buggy, but the initial load nonetheless. |
dgisselq |
3113d 22h |
/ |
