| Rev |
Log message |
Author |
Age |
Path |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3056d 01h |
/ |
| 30 |
Bug fixes. In particular, this fixes a segmentation violation. |
dgisselq |
3056d 05h |
/ |
| 29 |
This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v) |
dgisselq |
3056d 21h |
/ |
| 28 |
Oops--two files needed by zipdbg weren't originally placed in the directory. |
dgisselq |
3057d 01h |
/ |
| 27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
3057d 01h |
/ |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3057d 01h |
/ |
| 25 |
Fixing compile time warnings. |
dgisselq |
3057d 02h |
/ |
| 24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
3063d 00h |
/ |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3065d 11h |
/ |
| 22 |
Added the mkdatev.pl file. (Oops!) |
dgisselq |
3068d 04h |
/ |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3118d 10h |
/ |
| 20 |
Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board. |
dgisselq |
3118d 10h |
/ |
| 19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3118d 11h |
/ |
| 18 |
Got the bitfile back up to speed at 80 MHz. |
dgisselq |
3122d 01h |
/ |
| 17 |
Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...) |
dgisselq |
3122d 01h |
/ |
| 16 |
Updates to allow a test of the ICAP configuration interface. |
dgisselq |
3122d 01h |
/ |
| 15 |
WORKING VERSION! ... or, at least the memory test works. |
dgisselq |
3123d 21h |
/ |
| 14 |
Quick bug fix. |
dgisselq |
3123d 21h |
/ |
| 13 |
This version is now working. (It probably would've worked before, but
everything is now working.) |
dgisselq |
3123d 21h |
/ |
| 12 |
Modified to match the settings I'm now using within ISE. |
dgisselq |
3124d 00h |
/ |
